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Lattice Semiconductor
MAC Control Register (R/W)
Mnemonic: MACCNTL
POR Value = 00H
Application Support
Name
Rsvd [7:5]
ignore next packet
tx_fifo_empty
rx_fifo full
fifo control frame
send pause request
Range
7-5
4
3
2
1
0
Description
Reserved
ignore next packet : This bit asserts the ignore_next_pkt pin on the TSMAC
IP core. See Table 2-1 on page 14 for more information.
tx_fifo_empty : This bit gets ORed with the FIFO empty signal. The ORed
output sets the tx_fifoempty pin on the TSMAC IP core. See Table 2-1 on
page 14 for more information on this TSMAC IP core signal. Note by setting
this bit you can mimic the Tx FIFO being empty. Also note that the applica-
tion design only has one loopback FIFO. So the Tx FIFO is the same as the
Rx FIFO.
rx_fifo full : This bit gets ORed with the FIFO full signal. The ORed output
sets the rx_fifo_full pin on the TSMAC IP core. See Table 2-1 on page 14 for
more information on this TSMAC IP core signal. Note by setting this bit you
can mimic the rx fifo being full. Also note that the application design only has
one loopback FIFO. So the Tx FIFO is the same as the Rx FIFO.
fifo control frame : This bit sets the tx_fifoctrl pin on the TSMAC IP core.
See Table 2-1 on page 14 for more information on this TSMAC IP core sig-
nal.
send pause request : This bit gets ORed with the Tx FIFO almost full signal.
The ORed output sets the tx_sndpausreq pin on the TSMAC IP core. See
Table 2-1 on page 14 for more information on this TSMAC IP core signal.
When this bit is set High OR the FIFO is almost full tx_sndpausreq is
asserted, otherwise tx_sndpausreq is de-asserted.
Pause Timer Register - Low Byte (R/W)
Mnemonic: PAUSTMRL
POR Value = 00H
Name
pause timer Low bits
[7:0]
Range
7:0
Description
Pause Timer Low bits : These reg bits set the tx_sndpaustim[7:0] pins on
the TSMAC IP core. See Table 2-1 on page 14 for more information on this
TSMAC IP core signal.
Pause Timer Register - High Byte (R/W)
Mnemonic: PAUSTMRH
POR Value = 00H
Name
pause timer High bits
[7:0]
Range
7:0
Description
Pause Timer High bits : These bits set the tx_sndpaustim[15:8] pins on the
TSMAC IP core. See Table 2-1 on page 14 for more information on this
TSMAC IP core signal.
IPUG51_03.0, December 2010
53
Tri-Speed Ethernet MAC User’s Guide
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